The present invention relates to a semiconductor device such as a high voltage driver IC used for controlling and driving a power device.
Big tasks for an electric conversion device, such as an inverter used in power switching devices, are power consumption reduction, function enhancement, downsizing, cost reduction or noise reduction. In the field of a power module having been commercialized by combining IGBTs (Insulated Gate Bipolar Transistors) and FWDs (Free Wheel diodes), demand for an IPM (Intelligent Power Module) is increasing year by year. The IPM is a module mounted with intelligent functions such as over current detection and protection or overheating detection and protection and incorporating in a power module a microcomputer for carrying out an operation programming of an inverter and components of an interface with an IGBT (the components of the intelligent functions). Thus, an effort to downsize an inverter is made by mounting the IPM.
In an IPM, however, there was a problem in that integration of detection circuits or protection circuits, which had been previously formed outside of a power module, into the power module increases the number of components thereby increasing the size of the IPM and causing costs to rise. For solving the problem, a high voltage driver IC (an HVIC (High Voltage Integrated Circuit) having a function of a driver) has made its appearance in which circuits with driver functions of an upper and lower arms, having their respective IGBTs, of a power conversion device, and circuits having various kinds of protecting functions are mounted in one silicon chip. The high voltage driver IC itself has a structure that can ensure a high voltage of 600V or 1200V as an element breakdown voltage of an IGBT.
FIG. 5 is a diagram showing connection of an HVIC and IGBTs. As shown in FIG. 5, an HVIC 1 has a control unit 11, a low side gate driver (GDUL) 12, a level-shifter 13 and a high side gate driver (GDUH) 14. A low side level on/off signal outputted from the control unit 11 is inputted to the gate of a low side IGBT 21 through the GDUL 12. The low side level on/off signal is also converted into a high side level on/off signal by the level-shifter 13. The high side level on/off signal is inputted to the gate of a high side IGBT 22 through the GDUH 14. In FIG. 5, reference numerals 23 and 24 denote FWDs.
FIG. 6 is a diagram showing a schematic configuration of the high voltage level-shifter 13. As shown in FIG. 6, the high voltage level-shifter 13 has a configuration in which a level-shift resistor 18 is connected in series to the drain of a high voltage n-channel MOSFET (HVN) 17 with a configuration in which pinch resistance 16 is connected to the drain of an n-channel MOSFET 15. In FIG. 6, VDD, GND, VCC and OUT designate a low side power supply potential, the ground potential, a high side power supply potential and a floating potential, respectively. Reference characters IN and GATE designate a low side level on/off signal and a high side level on/off signal, respectively. Moreover, reference numerals 19a to 19d denote inverters.
For a structure isolating a high voltage section and a low voltage section from each other in the high voltage driver IC, a general structure is given as a self-isolation structure or a junction isolation structure, a structure using a p-n junction, or a dielectric isolation structure using a dielectric material such as SiO2. In the self-isolation structure, a p-substrate, for example, is used on the top surface of which an n-island region is formed in which a circuit such as a driver circuit formed by a CMOS is made incorporated. By providing an adequate voltage withstanding structure in the n-island region, the high voltage section and the low voltage section can be electrically isolated by p-n junction capacitance.
For the voltage withstanding structure, a RESURF (REduced SURface electric Field) structure is used for the purpose of reducing an electric field concentration at a p-n junction appeared on the surface of the substrate. When a reverse bias voltage is applied between the isolated n-region and the substrate, the depletion layer expands in parallel with the surface of the substrate at a parallel plate junction at the bottom of a planar junction. Compared with this, at an end section of the region, a depletion layer is generally hard to uniformly expand to make electric field liable to concentrate. Therefore, the impurity concentration of the n-region is determined lower to make the end section easily depleted. With the RESURF structure, electric field strength is made reduced, by which high voltage withstanding characteristics can be obtained.
FIG. 7 is a cross sectional view showing an example of a high side device structure. As shown in FIG. 7, in the top surface layer of a p-semiconductor substrate 31, an n-isolation-diffused region 32 of an n-well is selectively formed. The resistance component of the n-isolation-diffused region 32 becomes the above-explained pinch-resistor. In the top surface layer of the n-isolation-diffused region 32, a region with a lateral HVN 34 and a region with a lateral n-channel MOSFET (MVN) 35 and a p-channel MOSFET (MVP) 36 both used for forming circuits in the n-isolation-diffused region 32 are formed with a self-shielded interconnection 33 formed between the regions. On the outside of the n-isolation-diffused region 32 in the top surface layer of the p-semiconductor substrate 31, a p+-region 37 is formed. The p+-region 37 is normally made at the ground potential.
To the n-isolation-diffused region 32 having a voltage withstanding structure, a power supply voltage of a driving circuit of a high side IGBT is applied. Moreover, in the n-isolation-diffused region 32, a p-region is provided to which a reference voltage of the driving circuit is applied. The p-region is also connected to the emitter electrode of the high side IGBT. Therefore, at switching of the low side IGBT, violent fluctuation in the collector voltage of the low side IGBT causes accompanied abrupt variations dV/dt to appear in the emitter terminal of the high side IGBT. The variations dV/dt are applied to the HVIC with the magnitude thereof sometimes becoming up to on the order of 10 to 20 kV/μs.
When the junction capacitance between the n-isolation-diffused region 32 and the p-semiconductor substrate 31 is charged or discharged by the variation dV/dt, a displacement current flows. The displacement current, unless adequately treated, becomes a base current of a parasitic transistor with lateral elements formed in the n-isolation-diffused region 32 and possibly causes faulty operations of circuits or destruction of the element. As countermeasures against this, the following technologies by the inventors are made publicly known.
In a semiconductor device including a first region of a first conductivity type, a second region of a second conductivity type selectively formed in the surface layer of a first principal surface of the first region, a third region of the second conductivity type formed in the surface region layer of the second region and a fourth region of the first conductivity type selectively formed in the surface layer of the second region, the third region is arranged around the fourth region with the second region arranged between. Moreover, the semiconductor device is characterized in that the minimum distance (L: in units of μm) between the third regions positioned with the fourth region put between and the sheet resistance (Rs: in units of Ω/□) of the second region satisfy the relationship of L≦4400/Rs (see JP-A-2000-236067, for example). By thus selecting L and Rs, high dV/dt noise robustness against 40 kV/μs or more can be ensured.
In addition, like on the high side, an n-isolation-diffused region (see FIG. 3) is also formed on the low side. Thus, the displacement current also becomes the base current of a parasitic transistor formed by the high side n-isolation-diffused region 32, the p-semiconductor substrate 31 and the low side n-isolation-diffused region (see FIG. 3). Therefore, measures are necessary against faulty operations and destruction of circuits by the parasitic transistor operation. As a measure against this, there is a publicly known technology that will be explained in the following.
The semiconductor device according to the publicly known technology is characterized by including a semiconductor substrate of a first conductivity type, a semiconductor region of a second conductivity type on the semiconductor substrate, and a trench structure reaching the semiconductor substrate of the first conductivity type from the semiconductor region of the second conductivity type, the semiconductor region being separated by the trench structure into a first and second regions, at least one of the first and second regions having a first conductivity type MOS with its first conductivity type drain region and its first conductivity type source region formed in the one of the regions, and a first conductivity type region formed in the semiconductor region having a second conductivity type MOS with its second conductivity type drain region and its second conductivity type source region formed in the first conductivity type region (see, for example, JP-A-2004-6555 and U.S. Pat. No. 6,642,583). The trench structure thus formed can inhibit a parasitic transistor or a parasitic thyristor a parasitically formed in the semiconductor device from causing parasitic operation (a bipolar operation or latchup) by a switching operation of a large capacity power supply semiconductor such as an IGBT.
However, in each of the semiconductor devices disclosed in JP-A-2004-6555 and U.S. Pat. No. 6,642,583, although the trench structure is formed between the high side n-isolation diffused region and the low side isolation diffused region as a region for taking out a displacement current, there is a drawback in that the number of process steps for forming the trench structure increases thereby increasing the cost of the chip. Moreover, there is also another drawback in that, in order to secure a region in which the trench structure is formed for taking out a displacement current, the chip area increases which also results in an increase in expense of the chip.
In order to solve the problems about the above-explained problems, it would be desirable to provide a semiconductor device such as an HVIC having sufficient dV/dt robustness without causing an increase in cost.